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Design Verification Project: RISC-V CPU Design and WISC-SP16 CPU Verification
Design Verification Project: RISC-V CPU Design and WISC-SP16 CPU Verification
Core Tools: SystemVerilog, UVM, Waveform Viewer, Cocotb, Python
Core Tools: SystemVerilog, UVM, Waveform Viewer, Cocotb, Python
FPGA Prototyping Project: Quantum Computing Control and Readout Platform Prototyping using Xilinx ZCU-216
FPGA Prototyping Project: Quantum Computing Control and Readout Platform Prototyping using Xilinx ZCU-216
ECE554_Final_Report_Matmultitaskers.docx.pdf
Weeble Bot
Weeble Bot
A Novel Configuration Robot
A Novel Configuration Robot
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